1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to a low dielectric constant (low k) material used in an insulation layer of an integrated circuit structure wherein the low k dielectric material exhibits improved compatibility with conductive materials used as conductive fillers for vias/contact openings formed in the low k dielectric material, and to a method of making such improved low k dielectric material.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of interconnects, including metal interconnects, being placed closer together, as well as reduction of the horizontal spacing between metal lines on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled xe2x80x9cPursuing the Perfect Low-K Dielectricxe2x80x9d, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH3xe2x80x94SiH3) with hydrogen peroxide (H2O2) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400xc2x0 C. to remove moisture. The article goes on to state that beyond methyl silane, studies show a possible k of 2.75 using dimethyl silane in the Flowfill process. The Peters article further states that in high density plasma (HDP) CVD, dielectric material formed from methyl silane or dimethyl silane and O2 can provide a k as low as 2.75; and that trimethyl silane, available from Dow-Corning, can be used to deposit low-k (2.6) dielectric films.
An article by S. McClatchie et al. entitled xe2x80x9cLow Dielectric Constant Oxide Films Deposited Using CVD Techniquesxe2x80x9d, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H2O2 to achieve a dielectric constant of xcx9c2.9. The authors then further describe the formation of low-k dielectric material using dimethyl silane (CH3)2xe2x80x94SiH2, thereby achieving a dielectric constant of xcx9c2.75. However, the authors point out that the methyl silane and the dimethyl silane both result in carbon being bound into the oxide lattice via a Sixe2x80x94CH3 bond which results in the termination of the siloxane chain. The authors further state that the addition of further CH3 groups bound to the silicon atom is thought to be prohibitive because an increase in the number of CH3 groups reduces the number of sites available to form the siloxane chain. Instead, the authors reported taking a different approach by incorporating the carbon as part of the siloxane chain itself so that the siloxane chain would not be broken. The authors then report on the use of methylenebis-silane (SiH3xe2x80x94CH2xe2x80x94SiH3) instead of methyl silane as the precursor material reacted with H2O2 whereby the SiH3 functional groups can take part in the polymerization reactions with H2O2 leaving the Sixe2x80x94CH2xe2x80x94Si backbone intact as a part of the siloxane chain, and state that a dielectric material having a dielectric constant of xcx9c2.7 can be achieved by using methylenebis-silane in place of methyl silane as the precursor.
Attempts have been made to further lower the dielectric constant of the film by increasing the carbon content in the dielectric film using phenyl silane as the precursor. While a film having a low dielectric constant was obtained, using a phenyl silane precursor, the dielectric constant was found to vary from film to film with k values between xcx9c2.1 to xcx9c2.8, i.e., formation of a film with a given k value was not reproducible.
In Aronowitz et al. U.S. patent application Ser. No. 09/274,457, assigned to the assignee of this invention, and the subject matter of which is incorporated by reference into this application, a low dielectric constant carbon-containing silicon oxide dielectric material is described and claimed which is formed by reacting a mild oxidizing agent such as hydrogen peroxide with a multiple carbon-substituted silane having only primary hydrogens bonded to the carbon atoms in the multiple carbon-substituted silane precursor.
While these approaches have succeeded in lowering the dielectric constant (k) of the carbon-substituted silicon oxide dielectric material, and therefore lowering the capacitance of integrated circuit structures formed using such low k dielectric material, problems have been encountered with respect to contact openings and vias formed in such low dielectric material. Apparently the presence of carbon in the low k dielectric material renders the material more susceptible to damage during subsequent processing of the structure. For example, contact openings or vias are usually etched in the dielectric layer through a resist mask. When the resist mask is subsequently removed by an ashing process, damage can occur to the newly formed via surfaces of the low k material resulting in what is known as via poisoning wherein filler material subsequently deposited in the via, such as a titanium nitride liner and tungsten filler material, fails to adhere to the via surfaces.
Various approaches have been attempted to remedy the problem of via poisoning, including the use of special liners or the treatment of the via sidewall surfaces, either prior to the ashing step to prevent subsequent damage to the low k material surface in the via, or after the ashing step to attempt to repair the damaged surface of the low k material in the via.
Copending application Ser. No. 09/426,056, entitled xe2x80x9cLOW K DIELECTRIC COMPOSITE LAYER FOR INTEGRATED CIRCUIT STRUCTURE WHICH PROVIDES VOID-FREE LOW K DIELECTRIC MATERIAL BETWEEN METAL LINES WHILE MITIGATING VIA POISONINGxe2x80x9d, was filed by one of us with others on the same date as this application and is assigned to the same assignee as this application. The subject matter of Ser. No. 09/426,056 is also hereby incorporated by reference. In one embodiment in that application, a void-free low k silicon oxide dielectric material is formed in the high aspect regions between closely spaced apart metal lines by one of several processes, including the process used to form the first low k silicon oxide dielectric material described in the present application. A second layer of low k silicon oxide dielectric material is then deposited over the first layer and the metal lines by a process which deposits at a rate higher than the deposition rate of the void-free dielectric material. In a preferred embodiment, both of the layers are formed in the same vacuum chamber without an intervening planarization step.
Copending application Ser. No. 10/153,011 entitled xe2x80x9cINTEGRATED CIRCUIT STRUCTURE HAVING LOW DIELECTRIC CONSTANT MATERIAL AND HAVING SILICON OXYNITRIDE CAPS OVER CLOSELY SPACED APART METAL LINESxe2x80x9d was also filed by one of us with others on the same date as this application and is assigned to the same assignee as this application. The subject matter of Ser. No. 10/153,011 is also hereby incorporated by reference. In that application, a layer of silicon oxynitride (SiON) is formed over the top surface of the metal lines to serve as an anti-reflective coating (ARC), a hard mask for the formation of the metal lines, and a buffer layer for chemical mechanical polishing (CMP). Low k silicon oxide dielectric material having a high carbon doping level is then formed in the high aspect regions between closely spaced apart metal lines up to the level of the silicon oxynitride. CMP is then applied to planarize the upper surface of the low k carbon-doped silicon oxide dielectric layer, using the SiON layer as an etch stop, i.e., to bring the level of the void-free low k silicon oxide dielectric layer even with the top of the SiON layer. A conventional (non-low k) layer of silicon oxide dielectric material is then deposited by plasma enhanced chemical vapor deposition (PECVD) over the low k layer and the SiON layer. A via is then cut through the second dielectric layer and the SiON to the top of the metal line. Since the via never contacts the low k layer between the metal lines, via poisoning due to exposure of the low k layer by the via does not occur.
Thus it can be seen that reducing undesirable capacitance formed in an integrated circuit structure in a manner which does not give rise to the problem of via poisoning is a desirable goal.
Quite surprisingly, we have discovered that the capacitance of an integrated circuit structure may be lowered without encountering the problem of via poisoning by careful control of the carbon content of the carbon-containing low k silicon oxide dielectric material in two regions: a first region between adjacent raised conductive lines formed over an underlying insulation layer, where undesirable capacitance may be formed horizontally between such adjacent conductive lines; and a second region above the raised conductive lines where vias are normally formed extending upward from the raised conductive lines through the low k dielectric layer to an overlying layer of metal interconnects. In one embodiment, the carbon-containing low k silicon oxide dielectric material used in the first region between adjacent raised conductive lines has a high carbon content to provide maximum reduction of the dielectric constant of the dielectric material for maximum reduction in the horizontal capacitance developed between horizontally adjacent lines, while the carbon-containing low k silicon oxide dielectric material used in the second region above the raised conductive lines has a reduced carbon content to mitigate poisoning of vias formed through the dielectric material in this second region. In another embodiment both the first and second regions have the same or similar reduced carbon content in the carbon-containing low k silicon oxide dielectric material in both of the respective first and second regions.